Nanochip Technology

Nano-chip is developing the next generation of removable, portable memory chips for consumer, computer, and server applications. Using MEMS technology along with arrays of atomic force probe tips, Nano-chip is developing storage chips that will store tens of Gigabytes per chip. Our technology is not bound by lithography constraints so we will be able to offer storage chip products through our customers that will exceed 100 GB per chip set in the beginning and grow to Terabytes per chip set in the future.

Some nanotechnology firms are using carbon nano-tubes for the development of next-generation semiconductor devices. These devices include memory, logic, and other semiconductor products. In the field of memory, the latest achievement will be a high-density nonvolatile Random Access Memory {RAM}. The company's objective is to deliver a product that will replace all existing forms of memory, such as DRAM, SDRAM and flash memory, with this RAM serving as universal memory. The potential applications for the nonvolatile memory is developing are extensive and include the ability to enable instant-on computers and to replace the memory in devices such as cell phones, MP3 players, digital cameras, and PDAs, as well as applications in the networking arena. This RAM can be manufactured for both standalone and embedded memory applications.

The core technology contained in our memory chips is created by the use of arrays of atomic force probe tips to write, read, and record data bits on a continuous storage medium. Please reference below for a scanning electron microscope photo of one of our tips on the end of a cantilever. This tip has a radius of less than 25 nm when it comes in contact with the memory medium. A voltage is passed from the tip into the recording layer. This voltage changes the state of the memory medium. In the reading mode, a low voltage on the tip is used to sense the 1,0 state of the media without erasing or affecting the stored data.

The Nano-chips are assembled by wafer bonding a media wafer to a tip-array wafer. As seen in the drawing below, after the wafer bonding process, the Nano-chips will be diced and packaged. Writing, reading, and erasing are done while scanning the media platform in X and Y. This allows the tips to trace out a raster pattern across the media under each tip, similar to the raster scan pattern used by the electron beam in TVs.

* Aerial Density: All storage devices are ultimately limited in capacity by the aerial density of the bits stored, i.e. the number of bits per square inch that can be stored on a disc or in the total area of a semiconductor chip. In the removable storage chip market today, NAND flash is clearly the market leader in both chip volume and cost per Megabyte. The latest NAND flash chips use 65 nm li thography to define their bit cells and they typically store two data bits per cell using Multi-Level technology. With the present Nanochip probe tip technology used we typically record a single bit of data in a 15 nm by 15 nm area. The Nanochip scanning probe technology has a growth path that will lead us in the future to bit cells as small as 2 or 3 nm which will give us single memory chip of greater than 1 TB per die.

* Manufacturing cost: Today Nanochip uses one micron semiconductor fabs to make our MEMs chips. This type of equipment was used over ten years ago for most semiconductor products. Therefore, the cost of building a MEMs fab to make our chips is in the tens of millions of dollars, unlike the several billion dollars needed to make a 70 nm and soon a 45 nm semiconductor fabrication facility. Furthermore, we can use the same initial semiconductor/MEMS fab to make future generations of Nanochips since we have no requirements to change our lithography as we double density every year.

* Interfaces: Nanochip will use standard interfaces so that our customers and the end users can use our products in all consumer electronic devices, laptop computers, and enterprise servers.